Circuit arrangement for compensation of time of flight differences in clock synchronized data transfer, where data travels over varying path lengths and a time delay is determined for each data source based on a phase detector

摘要

Method for compensation of time of flight differences in which the data sources (Q1-Qn) are clock synchronized with a synchronization cycle (T) so that data can be transferred from them over data transfer paths (D1-Dn) that have different time of flights, to a data sink (S). To balance out the time of flight differences (time for data transfer), the differences are determined and a time delay applied to each transfer path so that data is synchronized. An Independent claim is made for a circuit arrangement with a number of clock controlled data sources with different length data transfer paths linking them to a data sink. Each data path has an associated time delay member (TV1-TVn) and a phase detector.