发明名称 |
Multiple module processing system with reset system independent of reset characteristics of the modules |
摘要 |
A reset module operates in conjunction with a system clock module to provide a combination of reset and clock assertions that can be relied upon to reset conventional processing modules having a variety of reset architectures. A reset command initiates an assertion of the reset signal and an activation of all clocks at the system level. After a predetermined number of clock cycles, the system level clocks are deactivated, and then the reset signal is de-asserted. By providing multiple clock cycles with the reset signal asserted, processing modules having either asynchronous and synchronous reset will be reset. By disabling the clocks before de-asserting the reset signal, the likelihood of a timing hazard caused by an interaction of the reset signal and a clocking signal is reduced or eliminated.
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申请公布号 |
US6480967(B1) |
申请公布日期 |
2002.11.12 |
申请号 |
US19990316783 |
申请日期 |
1999.05.21 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
JENSEN RUNE HARTUNG;GARTLAN MICHAEL |
分类号 |
G06F1/24;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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