CMOS compatible lateral DMOS transistor has drift space region depleted of free charge carriers if drain voltage lower than gate isolator breakdown voltage

摘要

The device has a region of the drift space near a highly doped surface zone or in a region bounding a highly doped region directly connected to a control gate that is totally free depleted of free charge carriers when a drain voltage lower than the gate isolator breakdown voltage is applied. The device has the entire surface of a drift space covered by a zone of the same conductor type as the drain region that is of low doping compared to the highly doped drain region and in which the area-related net doping concentration is not greater than 5 x 10<->12 At/cm<2>. The region of the drift space near a highly doped surface zone (9b) or in a region bounding a highly doped drain region (9) directly connected to a control gate (6) is totally free depleted of free charge carriers when a drain voltage lower than the gate isolator (5) breakdown voltage is applied. Independent claims are also included for the following: a method of manufacturing a CMOS compatible lateral DMOS transistor.