| 摘要 |
PURPOSE: A synchronous DRAM device having a posted CAS(Command Address Strobe) function of a JEDEC(Joint Electronic Device Engineering Council) standard is provided to increase efficiency of bus between a synchronous DRAM and an external controller and satisfy items desired for the posted CAS function of the JEDEC standard. CONSTITUTION: A command input pin(110) receives external command signals(/CS,/RAS,/CAS,/WE) of TTL level. The external command signals(/CS,/RAS,/CAS,/WE) of TTL level are converted to external command signals(/CS,/RAS,/CAS,/WE) of CMOS level by command input buffers(182,184,186,188). A command decoder(120) receives and decodes command signals(PCS,PRAS,PCAS,PWE) from command input buffers(182,184,186,188) and outputs decoded commands(PRAS_ACT,PREF,...,PREAD,PWRITE). A write command latency control portion(140) receives a write command from the decoded commands(PRAS_ACT,PREF,...,PREAD,PWRITE) and outputs a delay write command(PWA) in response to a predetermined latency control signal. A read command latency control portion(160) receives a read command(PREAD) from the decoded commands of the command decoder(120) and outputs a delay read command(PCA) in response to the predetermined latency control signal.
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