Function testing of hardware architectures, especially CPU and chipset, or multiprocessor computers, where the minimum number of test vectors to ensure a sufficiently small probability of errors is used

摘要

Method for functional testing of hardware architectures, in which, before and during operation, a cyclical data flow is produced that is used to test hardware using a semiconductor error model with test vectors. The test vectors are generated dependent on the functional and physical semiconductor structure of the function groups of the hardware architecture of the device under test. An Independent claim is made for a computer program for function testing of hardware architectures. The invention also relates to use of the method or computer program for testing hardware architecture of multi-processor computer systems.