发明名称 Automatic test equipment for semiconductor device
摘要 <p>Automatic test equipment for testing semiconductor devices equipment includes a) a clock; b) a delay line comprised of a plurality of delay stages (212), each delay stage (212) having an input and an output and a control input, with the input of the first delay stage (212(0)) coupled to the clock and the input of every other delay stage coupled to the output of the preceding stage in the delay line; said automatic test equipment characterised by: c) a phase detector (214) having a first input coupled to an output of a delay stage in the delay line and in an input coupled to the output of a prior delay stage in the delay line; and d) a control circuit (216) having an input coupled to the output of the phase detector and an output connected to the control inputs of each of the delay stages in the delay line. <IMAGE></p>
申请公布号 EP1146641(A1) 申请公布日期 2001.10.17
申请号 EP20010116911 申请日期 1998.07.22
申请人 TERADYNE, INC. 发明人 SARTSCHEV, RONALD A.;MUETHING, GERALD, F. JR.
分类号 G01R31/28;G01R31/3183;G01R31/319;H03K5/00;H03K5/13;H03L7/081;(IPC1-7):H03K5/13 主分类号 G01R31/28
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