发明名称 |
Method of forming MOS/CMOS devices with dual or triple gate oxide |
摘要 |
A method of fabricating multiple thickness gate oxide layers, comprising the following steps. A silicon substrate having at least a first and second gate oxide region is provided. A first gate oxide layer is formed over the silicon substrate within the first gate oxide region. The first gate oxide layer having a first predetermined thickness. A first layer of polysilicon is deposited and planarized over the first gate oxide layer. The first planarized layer of polysilicon and the first gate oxide layer are masked and etched within the second gate oxide region, exposing the silicon substrate within the second gate oxide region. A second gate oxide layer is formed over the exposed silicon substrate within the second gate oxide region. The second gate oxide layer having a second predetermined thickness. A second layer of polysilicon is selectively deposited over the second gate oxide layer. The first and second layers of polysilicon are planarized to a uniform thickness. Whereby the second gate oxide layer predetermined thickness is less than the first gate oxide layer predetermined thickness.
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申请公布号 |
US6268251(B1) |
申请公布日期 |
2001.07.31 |
申请号 |
US20000614556 |
申请日期 |
2000.07.12 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING INC. |
发明人 |
ZHONG DONG;ZHENG JIA ZHEN |
分类号 |
H01L21/8234;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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