Chip size package has all its silicon layer doped regions connected by structured conductor lines at the side at which the doped regions are introduced

摘要

A chip size package (CSP) has all its silicon layer doped regions (9) connected by structured conductor lines (3a) at the side at which the doped regions are introduced. A novel CSP comprises a silicon layer (1) in which all the doped regions (9) required for electrical functioning of the structure are provided, from above (i. e. from the side at which the doped regions are introduced into the active silicon layer), with one or more structured conductor lines (3a) which connect individual doped regions together in the active silicon layer, the layer being enclosed on all sides by a passivation layer (5) and having two or more bottom electrical connections (4). Independent claims are also included for the following: (i) a housed semiconductor structure comprising a stack of electrically connected CSPs as described above; and (ii) production of the above CSP. Preferred Features: The conductor lines (3a) consist of polysilicon, a silicide or tungsten and the passivation layer (5) consists of oxide, nitride and/or polyimide.