发明名称 CELL MULTIPLEXER CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a cell multiplexer circuit that an operating speed of an ATM switch or the like accommodating many high speed input channels is decreased to suppress the power consumption and the heat generation and the ATM switch can be mounted on a satellite of a multimedia satellite communciation system. SOLUTION: This cell multiplexer circuit 1 uses input sections 3a-3c to discriminate whether or not an arrived packet (cell) has a valid data part, to exclude packets having no valid data part and to store only packets having the valid data part to input buffers 2a-2c. In the case of reading packets from the input sections 3a-3c, a gate control section 5 transmits control information to gates in response to an amount of data of the packets stored in the input buffers 2a-2c and a gate control section 5 switches the gates in response to the control information so as to multiplex signals at a low common bus operating speed.</p>
申请公布号 JP2000278271(A) 申请公布日期 2000.10.06
申请号 JP19990082029 申请日期 1999.03.25
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 TOSHINAGA HIDENORI;OTSU TORU;KAZAMA HIROSHI
分类号 H04L12/28;(IPC1-7):H04L12/28 主分类号 H04L12/28
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