发明名称 Parallel processing system with efficient data prefetch and compilation scheme
摘要 A parallel processing system capable of facilitating the data prefetch in the parallel computer and realizing a compilation scheme capable of removing the overhead caused by the control codes due to the parallelism. In the system, data dependency of each operation in the program is analyzed. Then, according to the data dependency, each processor recognizes those processors which have possibilities to require data allocated to the distributed part of the distributed shared memory in each processor, and each processor transmits the data to these processors before these processors actually require the data. The system has a host side compiler for compiling each program such that parallel processing independent portions of the program are compiled up to object-codes, while leaving parallel processing dependent portions of the program as intermediate-codes, and a node side compiler at each processor for optimally compiling the object-codes and the intermediate-codes obtained by the host side compiler to obtain optimum execution codes, according to information concerning parallelism.
申请公布号 US6092097(A) 申请公布日期 2000.07.18
申请号 US19960592612 申请日期 1996.01.26
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SUZUOKA, TAKASHI
分类号 G06F9/45;G06F9/44;G06F15/16;G06F15/177;(IPC1-7):G06F15/16 主分类号 G06F9/45
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