发明名称 FAULT RESILIENT/FAULT TOLERANT COMPUTING
摘要 A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204). <IMAGE>
申请公布号 EP0731945(B1) 申请公布日期 2000.05.17
申请号 EP19950902615 申请日期 1994.11.15
申请人 MARATHON TECHNOLOGIES CORPORATION 发明人 BISSETT, THOMAS, D.;FIORENTINO, RICHARD, D.;GLORIOSO, ROBERT, M.;MCCAULEY, DIANE, T.;MCCOLLUM, JAMES, D.;TREMBLAY, GLENN, A.;TROIANI, MARIO
分类号 G06F11/18;G06F1/04;G06F1/14;G06F11/00;G06F11/14;G06F11/16;G06F11/20;G06F13/00;G06F13/10;G06F13/14;G06F15/16;G06F15/76;(IPC1-7):G06F15/16 主分类号 G06F11/18
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