发明名称 TESTING METHOD OF CHIP SCALE PACKAGE
摘要 PROBLEM TO BE SOLVED: To provide a testing method for CSP(chip-scale package), capable of avoiding the dislocation of solder to contact pins also facilitating the handling of the CSP. SOLUTION: In this testing method, Au-plated lands 7a are provided in a ball fitting hole 7 on a frame substrate 1 in the loading state of IC chips 2 so that the testing can be performed by bringing contact pins 6a into contact with these lands 7a later for fitting balls 3 to be cut into a final shape.
申请公布号 JP2000040721(A) 申请公布日期 2000.02.08
申请号 JP19980206202 申请日期 1998.07.22
申请人 MITSUBISHI ELECTRIC CORP 发明人 SHIGETOMO KUNIHIRO
分类号 G01R31/26;H01L21/66;(IPC1-7):H01L21/66 主分类号 G01R31/26
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