| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock generating circuit for generating a clock at any arbitrary frequency. SOLUTION: An input signal Si is converted to the pulse width of one cycle of a clock S11 by a pulse width converting part 12 and a reference signal S12 is outputted. When an enable signal S16a is valid, the frequency of the clock S11 is divided by a frequency dividing part 13 and a compare signal S13a is outputted. Besides, the clock S11 is counted by the frequency dividing part 13 and a count value S14b over the range of clock frequency setting information rt is outputted. The phases of the reference signal S12 and compare signal S13a are compared by a phase comparing part 14 and a phase difference number signal S14a and a phase difference direction signal S14b are outputted. A clock control part 15 outputs a clock control signal S15 based on the count value S13b, phase difference number signal S14a and phase difference direction signal S14b. A clock S16b and enable signal S16a of a frequency corresponding to the clock frequency setting information rt are outputted from a clock generating part 16. |
