| 摘要 |
PURPOSE:To reduce the circuitry of a divider and to make a divider high in dividing speed. CONSTITUTION:A control circuit 8 instructs the kinds of the calculation of an arithmetic circuit 2 (OPR), the number of shift of a first shifter 3 (SFT1) and the number of shift of a second shifter 5 (SFT2) based on the carry from the most significant bit of the arithmetic circuit 2 having the same bit width as that of a divisor register 1 (ACRY), the value of a shift overflow holding register 7 (SCRY) and the value of the least significant bit of the second register 6 (a partial quotient Q(n-1) one before) and generates the insertion value (a partial quotient Q(n)) to the least significant bit at the time of the one-bit shift of the second shifter 5. Thus, processing time is shortened and the scale of hardware is reduced. |
