| 摘要 |
A digitally compensated multi-bit sigma-delta analog-to-digital converter may be used to achieve high resolution in analog-to-digital conversions using a low oversampling ratio and simplified hardware construction. The digitally compensated multi-bit sigma-delta analog-to-digital converter has a recycling converter which converts an analog signal to a digital signal and which recycles the converted signal at least one time through a sample hold circuit, an analog-to-digital converter and a digital-to-analog converter in order to obtain a 4 bit digital signal. A digital corrector converts the 4 bit digital signal to a 16 bit corrected digital signal. The 16 bit corrected digital signal is used to generate a digitally compensated digital signal and to generate a digital error code. The digitally compensated digital signal is obtained by adding the 16 bit corrected digital signal with a 16 bit calibrated digital signal using an adder. The nine least significant bits of the compensated digital signal, representing a calibration value indicative of the error in the converted digital signal, are obtained using a roundoff circuit and stored in memory. As a result, high resolution in analog-to-digital conversion can be obtained while achieving a low oversampling ratio and simplified hardware construction.
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