| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of preventing erroneous writing by controlling the device so that the threshold voltage of a memory cell after erasing is not lowered into a prescribed voltage or lower. SOLUTION: A first sense latch circuit S/L1 is connected to bit lines BLE, BLO via transistors QNH3, QNL1 and a second sense latch circuit S/L2 is connected to the same via transistors QNH4, QNL2. After data of the memory cell are erased, an excessive erasion is detected and read, and the read data are latched to the first sense latch circuit S/L1. Whether an excessively erased cell exists or not is detected based on the latch data. In the case where the excessively erased cell exists, soft writing is executed and the threshold voltage is converged within a prescribed range.</p> |
