| 摘要 |
A b-bit digital and analog converter of the present invention is relatively simple and non-expensive and monotonic with relatively high differential and integral non-linearities. The converter uses weighed current ratio to achieve decrease the number of current cells to provide a cumulative current which corresponds to the digital value on the input data bus. The converter includes preferably a plurality of upper current cells, at least one unit current cell and at least one lower current cell. The currents produced by the upper, lower and unit current cells have a predetermined weighed current ratio, and the number of the upper, unit and lower current cells are based on the weighed current ratio. Further, the plurality of upper current cells have a prescribed layout, and includes a group of cells where each current cell has reverse layout orientation compared to adjacent cells.
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