| 摘要 |
PROBLEM TO BE SOLVED: To prevent a synchronization error from being caused even when a logical value change takes place between RDS bits. SOLUTION: Bits of an RDS signal and a bit transmission speed clock signal (BRC) are made up of two half bits having a different digital value being half bit pulses, a 1st or 2nd RDS half bit has a high level depending on either of the RDS bit of two logical values and the other RDS half bit has a low level, a digital value of the bit transmission speed clock signal is measured as a 1st sample value at a 1st time when at a rising or trailing of the bit of the RDS signal or in matching with the both, a digital value of the bit transmission speed clock signal is measured as a 2nd sample value at a 2nd time shifted from the 1st time by a delay time shorter than a half bit consecutive time, and a phase position of the bit transmission speed clock signal is shifted by a positive or negative phase angle being a prescribed phase angle depending on that the two samples are different or the same. |
