| 摘要 |
PURPOSE:To prevent excessive erase and to improve rewritability by connecting a word line to gate electrodes of memory transistors arranged in a row direction, connecting a bit line to a drain region of memory transistors arranged in a column direction, and connecting a source line commonly to a source region of each memory transistor. CONSTITUTION:A word line W1 is connected to memory transistor gates in memory cells 21A and 21B arranged in a row direction X, and a world line W2 is connected to memory transistor gates in memory cells 21C and 21D. A bit line B1 is connected to memory transistor drains in memory cells 20A and 20C arranged in a column direction Y, and a bit line B2 is connected to memory transistor drains in memory cells 20B and 20D. Also, a source line S is commonly connected to a memory transistor source in each of memory cells 20A to 20D, and a substrate line SUB to a substrate. This makes it possible to prevent excessive erase and to improve rewritable frequency. |
