| 摘要 |
A wide variety of integrated circuit applications exist for boosted nodes, wherein a voltage is boosted above the power supply level. Typical uses include clock driver circuits in microprocessors, row lines in dynamic and static memory chips, and substrate bias generators. However, in the prior art, only n-channel transistors have been usable to boost nodes above the positive power supply level, to prevent forward-biasing the drain-to-substrate diode. The present invention allows a p-channel device source/drain region to be connected to a boosted node. This is accomplished by also boosting the voltage of the n-tub in which the device is formed, thereby allowing the p+ source/drain regions to be boosted without latch-up or other problems. Similarly, n-channel devices may be connected to nodes boosted more negative than VSS.
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