发明名称 CHECKING PATTERN FOR LAYER ORGANIZATION OF MULTILAYER PRINT WIRING BOARD
摘要 PURPOSE:To surely find errors in layer organization of a board, relating to a checking pattern for layer organization of a multilayer print wiring board. CONSTITUTION:IVHs 11, 12,... dug to the depth of half way from surface layer substrates 1a and 1b to respective inner layer substrates 2, 3... and inner layer check patterns 32, 33... formed on the surfaces of the surface layer substrate 1 and respective inner substrates 2, 3,... are provided. And configuration is so made that these IVHs 11, 12,... are connected to the other only one inner layer check patterns, with respective inner layer check patterns 32, 33... being assigned to different IVHs 11, 12,... in normal layer organization.
申请公布号 JPH0621657(A) 申请公布日期 1994.01.28
申请号 JP19920178653 申请日期 1992.07.06
申请人 FUJITSU LTD 发明人 KOBAYASHI HIROSHI
分类号 G01R31/02;H05K3/46;(IPC1-7):H05K3/46 主分类号 G01R31/02
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