INTERLEAVED CACHE FOR MULTIPLE ACCESSES PER CLOCK IN A MICROPROCESSOR

摘要

An interleaved cache (500) for multiple data accesses per clock in a microprocessor. The cache includes a storage array having multiple banks of single-ported memory cells (505a - 505h) for storing data, a bank selector (503a - 503h) for selecting banks in the storage array simultaneously according to the multiple data accesses, and a datapath (U, VC-word lines) for transferring data between execution units in the microprocessor and the storage array. The cache of the present invention also includes contention logic (504) for prioritizing the multiple data accesses when multiple data accesses are to be same bank.