BIT-LINE ARRAY METHOD OF SEMICONDUCTOR MEMORY DEVICE

摘要

The method for increasing the pitch between sensing amplifiers and reducing the parasitic capacitance at sensing nodes to improve the sensing speed of the sensing amplifier comprises connecting at least two sensing amplifiers to each pair of bit lines, arranging the sensing amplifiers in the form of matrix, connecting the odd-numbered pairs of bit lines to the sensing amplifiers positioned at the intersections of the odd-numbered columns and even-numbered rows on the matrix, and connecting the even-numbred pairs of bit lines to the sensing amplifiers positioned at the intersections of the even-numbered columns and odd-numbered rows on the matrix.