Collector dot and circuit with latched comparator

摘要

A logic circuit which can operate to form a logic AND signal of a predetermined voltage level in accordance with a potential difference between a plurality of input signals using a collector dot AND circuit and a latched comparator circuit without the necessity of provision of a NOT circuit or a level shifting circuit at a preceding stage to the logic circuit. The logic circuit comprises a collector dot AND circuit, a logic level outputting circuit and a plurality of emitter follower circuits. Output electrodes of those of the emitter followers which are connected to receive NOT signals of input signals developed from the collector dot AND circuit are coupled commonly to form a wired OR circuit, and an output of the wired OR circuit is supplied to a transistor of the logic level outputting circuit connected to receive a logic AND signal of the input signals developed from the collector dot AND circuit so as to form a NOT signal of the logic AND signal.