| 摘要 |
<p>A memory management system for minimizing I/O data transfer latency during the resolution of page faults. A page protection register having a mask with validity bits corresponding to each data line of the page in local memory is implemented in the memory controller. The mask bits are set when the corresponding data line has been input via the memory controller and is ready for access. When a page fault is received by the microprocessor, the desired page is read into the microprocessor's local memory, and the mask bit corresponding to the critical line which caused the page fault is checked. Processing of the process which requested the critical data line proceeds as soon as the mask bit for the critical data line is set, thereby preventing the microprocessor from having to wait for the entire page to be transferred into local memory before processing continues. In addition, the invention provides a mechanism whereby the address of the critical data line is identified and provided to the external memory so that the data lines in the page may be sent out of order. In particular, the critical data line may be sent first so that it is the first data line stored in the local memory during memory I/O. The mask bits corresponding to the critical line are thus set first, thereby allowing the microprocessor to be quickly reactivated so that processing may proceed in parallel with I/O to the microprocessor's local memory. When the present invention is implemented for a page having N data lines, the data transfer latency time may be reduced by as much as a factor of N.</p> |
