发明名称 |
High-speed bit synchronizer |
摘要 |
A novel high-speed bit synchronizer circuit comprises a phase detector having two phase detecting loops, each adapted to generate a partial error voltage signal which is summed together to provide a single phase voltage error signal which is employed to control a VCO in the return branch of both phase detecting loops. Each phase detecting loop comprises a comparator coupled to the input data stream and to a reference voltage to provide two outputs. An electronic switch is coupled to the output of each comparator and each switch has its partial error voltage output coupled through a summing circuit to the VCO, thus completing two phase detecting loops each adapted to generate a partial phase error signal indicative of the phase error between the input data stream and the recovered clock output of the VCO.
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申请公布号 |
US5063577(A) |
申请公布日期 |
1991.11.05 |
申请号 |
US19890449683 |
申请日期 |
1989.12.12 |
申请人 |
UNISYS CORPORATION |
发明人 |
ARBANAS, GLENN A.;THORNOCK, JEFFERY M.;KEATE, CHRISTOPHER R. |
分类号 |
H03L7/087 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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