| 摘要 |
PURPOSE:To improve the transmission speed by using a data part subjected to RZ coding and generating a clock signal, thereby applying bit synchronization. CONSTITUTION:A CPU 40 retrieves whether or not a frame synchronization code is detected when the interruption by a clock CK takes place and when the frame synchronization code is detected, the CPU 40 is in the data reception mode thereafter and the data is received every time interruption by the clock signal CK takes place. When the production of data error is detected, the CPU 40 terminates the data reception mode immediately and awaits the arrival of a new frame synchronization code again. The correct data reception is started when the succeeding correct frame synchronization code reaches. |
