Array processor

摘要

A four stage pipelined processor (40) provides efficient processing of the most common operation performed in simulating neuron networks. A first stage of the processor includes a program memory (42) and a program address generator (41). A second stage comprises first and second data memories (44, 46) and respective address generators (60, 66) coupled thereto. A third stage comprises the input (X, Y) of a function unit (82), and a fourth stage comprises the output (Z) of the function unit (82). A unique bus architecture allows the various stages to simultaneously communicate with each other through the use of independent buses, and further provides for the quick simultaneous transfer of data from both the first and second data memories to the function unit. When not needed for performing in the pipelined mode, the various buses may be coupled together and to an I/O interface (52) by means of bus coupling means (e.g., 47). This architecture significantly reduces the circuitry needed to implement the necessary buses while allowing the processor to run without speed limitations in the pipelined mode.