| 摘要 |
PURPOSE:To attain fast discrimination of presence of a clock signal and to use the title circuit with no adjustment by providing a delay circuit retarding the clock signal and an OR gate ORing retarded clock signals. CONSTITUTION:Signals D1,D2 being the result of retarding a clock signal CK properly are outputted from a delay circuit 2. The signals D1, D2 are given to an OR gate 3. Thus, when the clock signal CK is inputted, since either of signals given to the OR gate 3 is logic 1, the output of the OR gate 3 goes to logic 1 and the input of the clock signal CK is discriminated. When the input of the clock signal CK is lost, the output signal of the delay circuit 2 goes to logic 0 and then the output of the OR gate 3 goes to logic 0, resulting that the absence of the input of the clock signal CK is discriminated. Thus, the discrimination of the absence of the clock signal is implemented quickly with no adjustment. |
