| 摘要 |
<p>This invention provides a static semiconductor memory device comprising, a plurality of static memory cells (10) for data storage, bit lines (11A, 11B) connected to the memory cells (10) for transferring data to and from the memory cells (10), a sense amplifier (17) having an input terminal, for amplfying the potential of the bit lines (11A, 11B) when data is transferred from the memory cells (10), and potential lowering device (30A, 30B) connected to the input terminal for lowering the potential of the input terminal of the sense amplifier (17) to a potential corresponding to substantially the optimum sensitivity of the sense amplifier (17) for increasing the speed of data transfer in the memory device.</p> |
