发明名称 DATA CONTROLLER
摘要 PURPOSE:To simplify the circuit constitution by giving the output of a processing circuit to a memory at least as a part of data designating a preliminarily determined address and outputting contents of a store area in the designated address of the memory. CONSTITUTION:When 100Hz tone signal is led out to a line 17, a processing circuit 18 sets an output terminal C0 to logical '1'. Then, the address of a store area M2 in a memory 21 is designated, and a signal of logical '1' from an output terminal D7 is led out to a line 19 to make a switch 13. If it is necessary that the line 19 is set to logical '1' to make the switch 13 when the tone signal is absent, data in store areas M1 and M2 in the memory 21 are rewritten. When receiving 100Hz tone signal from the line 17, the processing circuit 18 leads out the signal of logical '1' from the output terminal C0; and consequently, the address of the store area M2 in the memory 21 is designated, and logical '0' is led out from an output terminal D7 in accordance with this address designation to break the switch 13.
申请公布号 JPS631123(A) 申请公布日期 1988.01.06
申请号 JP19860143777 申请日期 1986.06.19
申请人 FUJITSU TEN LTD 发明人 AKAGI MORISHIGE;ENDO KAZUO
分类号 H04Q7/06;H04B1/10;H04B7/26;H04Q1/30;H04Q7/12;H04Q7/14 主分类号 H04Q7/06
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