| 摘要 |
PURPOSE:To eliminate the phase dislocation of both synchronizing signals by resetting a frequency divider when the phase difference between an internal horizontal synchronizing signal and an input horizontal synchronizing signal which are obtained by frequency-dividing an output signal from a voltage controlled oscillator exceeds the allowable value. CONSTITUTION:A horizontal synchronizing signal HS of 15.75kHz and an internal horizontal synchronizing signal IHS of 15.75kHz, in which an internal clock signal CL of 9.8MHz is frequency-divided into 624 by a counter 27, are inputted to a synchronizing circuit 29. When it is judged that these phase dislocations exceed the allowable value, the synchronizing circuit 29 sends a resetting signal RES to the counter 27 and clears the counter 27. The resetting signal RES is generated depending upon the timing of the horizontal synchronizing signal HS, and thus, the phase of the internal horizontal synchronizing signal IHS and the horizontal synchronizing signal HS, is matched which are outputted from the counter 27.
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