| 摘要 |
<p>PURPOSE:To generate a clock pulse having stable optional phase difference to an input clock pulse by determining suitably a reference voltage level to compare with a saw wave signal. CONSTITUTION:An input clock pulse k0 is frequency-divided to two timing signals Q and Q and saw wave signals Va and Vb are generated by two timing signals. Based upon the maximum value voltage of one side saw wave signal, a reference voltage level to partially pressure it and a saw wave signal generated by other side timing signal are compared by the voltage. Thus, a clock pulse generating circuit to generate plural clock pulses having the stable phase difference can be realized.</p> |
