| 摘要 |
<p>To reduce the parasitic capacitance due to the graft base area in a transistor device and to miniaturize the device, the graft base area is connected to a conductive layer (9) to be connected to the base electrode through a minute gap of about 1,000 λ. This minute gap can be formed by leaving an oxide resistant layer (18) (1,000 A) at the side wall portion of the conductive layer (9) of which peripheral portion is perpendicular to the surface of the base area by applying an isotropic etching technique and by removing the remaining oxide resistant layer on the basis of selective etching technique, after thermal oxidation of the device with masking the side wail portion by the remaining oxide resistant layer.</p> |
