| 摘要 |
<p>An integrated circuit (30) and method for biasing an impurity region, in particular an epitaxial layer (32), to a level substantially equal to a supply voltage level (Vcc) yet exhibiting a high reverse breakdown voltage to negative transients of the supply voltage (Vcc). The integrated circuit (30) and method is of especial utility in power BIMOS and other applications having the substrate (12) at or near the supply voltage level Vcc.</p> |
