| 摘要 |
PURPOSE:To reduce the instruction processing delay due to the register conflict by using a processor which is independent of a primary pipeline to read out an operand in a register conflict mode earlier than the processing of the primary pipeline. CONSTITUTION:An advance instruction register, i.e., a primary logic is set to a vertical axis together with a read-out action of the advance data, i.e., a primary action, the transfer of advance data and the read-out of an associative storage. The register conflict occurs in the first C7 cycle and an instruction address of an L instruction of the instruction No. 1 serving as an advance instruction is registered to an associative storage. Hereafter an instruction train of 16 bytes is set to an instruction buffer in a CO cycle in the second and subsequent time charts. At the same time, the L instruction of the instruction No. 1 is segmented from the instruction buffer by a predecoding action and set to an advance instruction register in a C1 cycle. At the sane time, it is detected that the L instruction produces an overhead by the register conflict. Thus the processing of an A instruction of the instruction No. 2 can be started in a C4 cycle.
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