| 摘要 |
PURPOSE:To increase the capacity of a MOS capacitor without increasing a chip size and to microminiaturize a cell and to increase the capacity by composing one electrode of the capacitor of the first layer electrode film formed with a recess and a flat portion, and burying the recess with an insulating film, flattening its. CONSTITUTION:An element forming region of a substrate 11 is coated with a mask 12, a taper is formed on the Si substrate 11 of a field region 13, etched, ion implanted to form a P<+> type layer 14. An SiO2 film 15 is buried in the region 13, an N<-> type layer 16 is formed on a MOS capacitor forming region, the side wall of the recess of the region 13 is formed in a Hi-C structure, and a depletion layer capacity between the layer 16 and the substrate 11 is increased. Then, the first gate oxide film 17 is formed on an element forming region, the first polycrystalline Si film 18 is accumulated on the overall surface, patterned, the second SiO2 film 19 is buried in the recess of the region 13, and the surface is flattened. Thus, a capacitor is formed on the side wall of the recess of the region 13 to largely increase the capacity. |
