| 摘要 |
A phase detector for use with a phase locked loop where the input has missing pulses. The detector processes two input frequencies and generates either a pump-up or a pump-down signal on separate outputs. The reference input may have missing transitions, as often happens in recovering the clock from encoded data. The phase detector comprises three bistable flip-flops and a gate interconnected to respond to the two input frequencies to produce either a pump-up pulse of variable width proportional to the phase difference between the pulses of the two input frequencies or a fixed width pump-down pulse.
|
