| 摘要 |
PURPOSE:To simplify the titled circuit by decreasing the area of the source and drain of an NMOSFET to 1/K of the area of the source and drain of a PMOSFET to compensate an offset voltage with high accuracy. CONSTITUTION:N channel FETQ1, Q3 and P channel FETQ2, Q4 are provided and the area of the drain and source of Q1-Q4 is decided so that the drain bulk capacitance and the source bulk capacitance of the Q1, Q3 are made substantially identical with those of the Q2, Q4. In this case, the surface area of the source and drain region of the Q1, Q3 is decided to 1/K times that of the source and drain region of the Q2, Q4. As a result, the total amount of electric charge generated based on the parasitic capacitance of the Q2 and the total quantity of electric charge for correction generated by the capacitance of the Q3 are made equal and no offset voltage compensation circuit is required. |
