DYNAMIC STORAGE DEVICE

摘要

PURPOSE:To attain a device with low power consumption, by inserting a level shift semiconductor element between a bit line and a sense circuit, limiting the range of voltage change at refresh of the bit line and decreasing the charge/ discharge energy. CONSTITUTION:When a sense signal phiSA goes to a low voltage VSS, the potential of the bit line d1 remains at a high voltage VDD, but that of the bit line d2 is decreased. Even if the output of a sense circuit SA goes to the low voltage VSS, since a transfer gate transistor(TR) Q10 exists, the potential of the bit line d2 is decreased only to (VSS+VT10) because the potential of the bit line d1 is a high voltage VDD. Since the bit line d1 is the high voltage VDD, the high voltage VDD is written in a capacitor C1. Further, since the potential of the bit line d2 is (VSS+VDD), the potential written in a capacitor C2 is (VSS+VDD) at VT2=VT10.