发明名称 Selectively operable bit-serial logic circuit
摘要 A logic circuit arrangement providing logical operations on serial data. The clock-controlled arrangement can transfer data bits internally either unchanged or subject to selected logical action and can thereby perform combinational and sequential logic on data bits, or resultant outputs, transferred at different points in time. In one form using semiconductor techniques a circuit arrangement (FIG. 11) is operated by mode controls M and clock controls C to transfer data bits unchanged or subject to logical action from inputs D, D to outputs Q, Q. A return signal path providing a time interval (FIGS. 3 and 4) and a mode controlled forward signal path (FIGS. 3 and 4) form a typical arrangement in which each clock signal processes an input data bit.
申请公布号 US4399377(A) 申请公布日期 1983.08.16
申请号 US19800114320 申请日期 1980.01.22
申请人 NATIONAL RESEARCH DEVELOPMENT CORPORATION 发明人 JONES, EDWIN V.
分类号 H03K3/037;H03K19/173;H03K19/21;(IPC1-7):H03K19/20;H03K19/00;H03K19/08;H03K19/17 主分类号 H03K3/037
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