| 摘要 |
PURPOSE:To obtain a multiplying circuit where the response is improved throughout a wide band, by presetting a counter with the measured value of the period of a fluctuated input signal to obtain a desired multiplication output. CONSTITUTION:The period of an input signal is measured and is stored in a period data register 13, and its fraction is stored in a period fraction data register 14. Contents of the register 13 are inputted to the first register 17 through the first adding circuit 15, and a period counter 19 is preset with the output of the register 17. The counter 19 counts clocks from a master clock oscillator 20 to output a desired multiplied output. Contents of the register 14 are added to preceding data in the second adding circuit 16, and the carry output is added to the adding circuit 15. The ouput of the adding circuit 16 is applied to the second register 18, and a delay circuit 21 is controlled by contents of the register 18 to restrict the phase. Input pulses from a terminal 8 are outputted in accordance with multiplication ratios by the output of an input pulse controlling circuit 23 to prevent the phase shift between the input and the output. |
