| 摘要 |
PURPOSE:To reduce the maximum frequency dividing number of a programmable frequency divider, by providing a means dividing the input signal or the output signal of the programmable frequency divider in terms of frequency. CONSTITUTION:A programmable frequency divider 2 divides the output signal of a clock signal generating circuit 1 by a frequency dividing number set by a setting circuit 3, and the output signal of the frequency divider 2 is converted to a signal of 50% duty cycle by a 2 frequency dividing circuit 4. A clock signal varying circuit 5 selects whether the output of the clock signal generating circuit 1 is applied to the frequency divider 2 after being divided to 1/M or is applied to the frequency divider 2 as it is; and when the frequency difference between adjacent frequencies of the frequency divider 2 is the 1/M of allowable frequency deviation, the clock signal is divided to 1/M and is applied to the frequency divider 2. Since the frequency dividing number of the frequency divider 2 is 1/M, the maximum frequency dividing number becomes small. |
