| 摘要 |
PURPOSE:To operate the output circuit at an early timing to make the operation high-speed, by driving the output circuit by the inversion signal of a short delay time and by driving the circuit for bootstrap by the inversion signal of a long delay time. CONSTITUTION:The output circuit of the address decoder circuit is formed by depletion loas MISFETQ1 and enhancement driving MISFETs Q2-Q4 to which address input signals ao-an are input respectively. The inverting circuit which inverts the address decoder output in a high speed is formed by FETQ9 and FETQ10. Then, push-pull output MISFETs Q15 and Q14 constituted by enhancement MISFETs which form the output signal are driven by the inversion output and the decoder output. |
