| 摘要 |
PURPOSE:To increase the effect of jitter compression, by controlling the output clock of a phase control circuit at leading and trailing point of input data. CONSTITUTION:The 0 phase clock nBc is fed to a shift register 13 constituting a frequency divider. When the input data 101 is input to FF1, the pi phase clock nBc is transferred to the shift register 13 at an earlier time from an AND circuit 18, and control is made so that the advance is made by a half phase of the pi phase after the conversion point of input data, allowing to cause the effect of compression by this share. The trailing pulse of the input data 101 is compared with the clock 116 of the register 13 and the AND circuit 17 to obtain the clock which is delayed by a half phase of the pi phase at the trailing and leading points of the input data at the output of an NAND circuit 10, and delayed clock is obtained at the terminal Qi frequency-divided. |
