发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To make circuit constitution simple with its circuit function simplified, by making processes in different data formats by the same arithmetic instruction word possible and by making it possible to separate a process in a single data format from that in several formats at need. CONSTITUTION:When an arithmetic instruction is executed, main arithmetic unit 2 and sub-arithmetic unit 6 decode the instruction simultaneously and then start the arithmetic execution. At this time, a signal is outputted, which indicates the ineffectiveness of the arithmetic execution and the stop of the next operation until the end of the arithmetic execution by sub-arithmetic unit 6, from main-arithmetic- unit control circuit 5 of sub-arithmetic unit 6 to main arithmetic unit 2. Namely, when the execution of an instruction for the selection of a data format is done prior to the execution of the arithmetic instruction, main-arithmetic-unit control circuit 5 in the operation mode of sub-arithmetic unit 6 to process following arithmetic instructions, thereby obtaining results while sub-arithmetic unit 6 whose execution time is long for synchronization between both arithmetic units 2 and 6 sends out a stop signal to main arithmetic unit 2.
申请公布号 JPS54122052(A) 申请公布日期 1979.09.21
申请号 JP19780030171 申请日期 1978.03.15
申请人 NIPPON ELECTRIC CO 发明人 UCHIDA AKIO
分类号 G06F7/00;G06F9/38 主分类号 G06F7/00
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