| 摘要 |
<p>A protective circuit for short circuit and overload protection of a power circuit, particularly integrated power circuits, in which the input of the final stage of such power circuit is controlled over an AND gate having a second input connected to the output of a flip-flop circuit. The latter is set by a pulse generator to close the input circuit of the final stage and in case of an overload the flip-flop is reset in response to an overload sensor, whereby the AND gate is blocked, and the final stage input circuit opened, during the pulse intervals as long as such overload exists.</p> |
