发明名称 Methods, systems, and computer program product for an integrated circuit package design estimator
摘要 Disclosed are mechanisms for implementing an IC package layout design with an integrated circuit package design estimator. These mechanisms determine an estimated number of layers for an integrated circuit (IC) package design including one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for the IC package layout design, determine a power layer and/or a ground layer based in part or in whole upon one or more factors, and generate an output for the IC package layout design based using at least the estimated number of layers and the power layer and/or the ground layer. These mechanisms use input including connectivity information, thermal effects, and/or IC placement information to determine estimates for the total number of layers, layer stack-up, power and ground plane assignment, and via libraries to guide IC package layout design.
申请公布号 US9454634(B1) 申请公布日期 2016.09.27
申请号 US201414588279 申请日期 2014.12.31
申请人 Cadence Design Systems, Inc. 发明人 Kukal Taranjit Singh;Singh Surender;Singh Avinash
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Vista IP Law Group, LLP 代理人 Vista IP Law Group, LLP
主权项 1. A computer implemented method for implementing an IC package design with an integrated circuit package design estimator, comprising: determining an estimated number of layers for an integrated circuit (IC) package design that includes one or more IC die designs with a layer and stack-up estimation mechanism comprising at least one processor that identifies the IC package design and determines the estimated number of layers for the IC package design; determining whether the estimated number of layers suffice to accommodate routing demands for interconnections between the IC package design and the one or more IC die designs with the layer and stack-up estimation mechanism; determining a power layer or a ground layer based in part or in whole upon one or more factors with a power and ground plane estimation mechanism; and generating an output for the IC package design with a guideline and scheme generation mechanism that functions in conjunction with the at least one processor that generates the output with at least the estimated number of layers and the power layer or the ground layer.
地址 San Jose CA US