发明名称 |
Method for via plating with seed layer |
摘要 |
Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening. |
申请公布号 |
US9640431(B2) |
申请公布日期 |
2017.05.02 |
申请号 |
US201615138033 |
申请日期 |
2016.04.25 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Yang Shin-Yi;Yeh Ching-Fu;Kuo Tz-Jun;Lee Hsiang-Huan;Lee Ming-Han |
分类号 |
H01L21/44;H01L21/768;H01L21/288;C25D7/12;C25D3/38 |
主分类号 |
H01L21/44 |
代理机构 |
Slater Matsil, LLP |
代理人 |
Slater Matsil, LLP |
主权项 |
1. A method of forming a structure, comprising:
forming an opening in a material layer; lining the opening with a metallic protection layer; and simultaneously removing the metallic protection layer and depositing a conductor in the opening. |
地址 |
Hsin-Chu TW |