| 发明名称 | Apparatus and method for heterogeneous processors mapping to virtual cores | ||
| 摘要 | A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software. | ||
| 申请公布号 | US9639372(B2) | 申请公布日期 | 2017.05.02 |
| 申请号 | US201213730565 | 申请日期 | 2012.12.28 |
| 申请人 | INTEL CORPORATION | 发明人 | Narvaez Paolo;Srinivasa Ganapati N.;Gorbatov Eugene;Subbareddy Dheeraj R.;Naik Mishali;Naveh Alon;Prabhakaran Abirami;Weissmann Eliezer;Koufaty David A.;Brett Paul;Hahn Scott D.;Herdrich Andrew J.;Iyer Ravishankar;Chitlur Nagabhushan;Sodhi Inder M.;Khanna Gaurav;Fenger Russell J. |
| 分类号 | G06F9/30;G06F9/38 | 主分类号 | G06F9/30 |
| 代理机构 | Nicholson De Vos Webster & Elliott LLP | 代理人 | Nicholson De Vos Webster & Elliott LLP |
| 主权项 | 1. A processor comprising: a set of one or more large physical processor cores including all of large physical processor cores of the processor; a set of one or more small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores, the set of one or more small physical processor cores including all of small physical processor cores of the processor; and a virtual-to-physical (V-P) mapping circuit to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor cores from the software. | ||
| 地址 | Santa Clara CA US | ||